Redressing timing issues for speed-independent circuits in deep sub-micron age

Abstract

With continued advancement in semiconductor manufacturing tech- nologies, process variations become more and more severe. These variations not only impair circuit performance but may also cause po- tential hazards in integrated circuits (IC). Asynchronous IC design, which does not rely on the use of an explicit clock, is more robust to process variations compared to synchronous design and is suggested to be a promising design approach in deep-submicron age, especially for low-power or harsh environment applications. However, the correctness of asynchronous circuits is also becoming challenged by the shrinking technology. The increased wire delays compared to gate delays and threshold variations could bring glitches into the circuit. This work proposes a method to generate a set of su cient timing constraints for a given speed-independent circuit to work correctly when the isochronic fork timing assumption is lifted into a weaker timing assumption. The complexity of the entire process is polyno- mial to the number of gates. The generated timing constraints are relative orderings between the transition events at the input of each gate and the circuit is guaranteed to work correctly by ful lling these constraints under the timing assumption. The benchmarks show that both the number of total constraints and the constraints that are only needed to eliminate strong adversary paths are reduced by around 40% compared to those suggested in the current literature, thus claiming the weakest formally proved condi- tions.