Full duplex-transceivers : architectures and performance analysis

Abstract

The revolution of the 5G communication systems will result in 10,000 times increase in the total mobile broadband traffic in the 2020s, which will increase the demand on the limited wireless spectrum. This has highlighted the need for an efficient frequency-reuse technique that can meet the ever-increasing demand on the available frequency resources. In-band full-duplex (FD) wireless technology that enables the transceiver nodes to transmit and receive simultaneously over the same frequency band, has gained tremendous attention as a promising technology to double the spectral efficiency of the traditional half-duplex (HD) systems. However, this technology faces a formidable challenge, that is the large power difference between the self-interference (SI) signal and the signal of interest from a remote transceiver node. In this thesis, we focus on the architecture of the FD transceivers and investigate their ability to approximately double the throughput and the spectral efficiency of the conventional HD systems. Moreover, this thesis is concerned with the design of efficient self-interference cancellation schemes that can be combined with the architecture of the FD transceiver nodes in order to effectively suppress the SI signal and enable the FD mode. In particular, an orthogonal frequency-division multiplexing (OFDM) based amplify-and-forward (AF) FD physical-layer network coding (PLNC) system is proposed. To enable the FD mode in the proposed system, a hybrid SIC scheme that is a combination of passive SIC mechanism and active SIC technique is exploited at each transceiver node of that system. Next, we propose an adaptive SIC scheme, which utilizes the normalized least-mean-square (NLMS) algorithm to effectively suppress the SI signal to the level of the noise floor. The proposed adaptive SIC is then utilized in a denoise-and-forward (DNF) FD-PLNC system to enable the FD mode. Finally, we introduce a novel overthe- air SIC scheme that can effectively mitigate the SI signal before it arrives the local analog-to-digital converter (ADC) of the FD transceiver nodes. Furthermore, the impact of the hardware impairments on the performance of the introduced SIC scheme is examined and characterized.