4H-SiC metal oxide semiconductor devices

Abstract

Metal oxide semiconductor (MOS) devices are the most important component in advanced integrated circuits (ICs). The success of Si in CMOS technology is owing to the excellent interface formed between Si and SiO2. However, Si-based electronic devices are not suitable to operate in high power, high frequency and high temperature conditions due to material limitations. 4H-SiC with a wide bandgap, high critical electric field, high thermal conductivity and high saturation drift velocity, is an attractive semiconductor material for extreme conditions. However, high quality oxide-semiconductor interfaces are still a major challenge in 4H-SiC MOS devices. This thesis focuses on interface studies of 4H-SiC MOS devices. The main aim is to produce high quality oxide/4H-SiC interfaces by the introduction of an ultrathin SiO2 layer between deposited oxides and 4H-SiC. Ultrathin SiO2 layers can be grown on 4H-SiC using a low thermal budget technique followed by Al2O3 deposition using ALD. N-type and p-type MOS capacitors were fabricated using a gate oxidation of 600 °C for 3 min, which produced SiO2 of thickness 0.7 nm as estimated using ARXPS. Electrical characterisation demonstrates an interface trap density (Dit) of 4-6 × 1011 cm-2eV-1 at 0.2 eV from the conduction and valence band edges. This represents a reduction in Dit by 1-2 orders of magnitude compared to the devices fabricated at 1150 °C for 180 min in the furnace. Furthermore, field effect channel mobility as high as 125 cm2/V.s and a subthreshold slope of 130 mV/dec were obtained from MOSFETs using similar gate stacks. The mobility of MOSFETs decreases with increasing temperature indicating that the electron conductivity is limited by phonon scattering rather than Coulomb scattering, and proves that Dit at the oxide/4H-SiC has been reduced. The ultrathin layer is believed to be a good interface layer between Al2O3 and 4H-SiC. As the temperature and time of the oxidation process increased, resulting in thicker SiO2, the values of Dit increased for both p-type and n-type MOS capacitors. Ultrathin SiO2 layers were also grown underneath a deposited SiO2 layer by N2O annealing at 1175 °C. From n-type MOS capacitor results, the lowest values of Dit obtained were 1.7 × 1012 cm-2eV-1 at 0.2 eV below the conduction band edge, for gate oxides consisting of 60 nm deposited SiO2 followed by 90 min of N2O annealing. This process produced a SiO2 layer 0.68 nm thick, estimated using the Deal-Grove model. The values of Dit increased as the grown SiO2 thicknesses became thicker or thinner than 0.68 nm. This trend is similar to what ii was found in ultrathin SiO2/Al2O3 gate stacks of MOS capacitors proving that 0.7 nm thick is the best thickness of SiO2 to use for 4H-SiC MOS devices. Electrical measurement up to 300 °C proved that these fabricated MOS devices are able to operate well at high temperature. MOSFETs utilizing ultrathin SiO2/Al2O3 gate stacks could retain their enhancement mode behaviour even at high temperature demonstrating the devices capability to be operated in extreme conditions. Both gate stacks also exhibited a low leakage current and were able to withstand electric fields far above 3 MV/cm, which is needed for actual operating system. The scope of these findings points to solutions for the interface challenges in 4H-SiC MOS devices. A thermally grown SiO2 layer 0.7 nm thick exhibited the lowest Dit values for both gate stacks and also produced high field effect channel mobility in MOSFETs. It is anticipated that this fabrication approach will mitigate the oxide/4H-SiC interface problem and contribute towards the development of improved power electronic devices.