Voltage Balancing Sorting Algorithm with Reduced Switching Frequency for Modular Multilevel Converters

Abstract

Over the last decade, Modular Multilevel Converters (MMCs) have been developed for medium- to high-voltage applications. They exhibit distinct features such as modularity, scalability, high degrees of redundancy and high-quality output voltage with the superior harmonic performance that reduces the requirement for filters. These features are unique to MMCs, thereby giving them a competitive advantage as an industrial solution over other voltage source multilevel converters. However, there are challenges associated with such converters when numerous submodules (SMs) are considered. The issues involved include voltage-balancing of the distributed SM, circulating current suppression, reliability, and increased complexity in the circuit configuration. The focus of this research is the voltage balancing of SMs. The most common and effective method of voltage-balancing is based on the well-known sorting algorithm, which results in higher switching frequency compared to other methods. This leads to substantially higher switching losses and hence lower efficiency, particularly when there are high numbers of SMs. Furthermore, the increased execution and calculation time leads to high computational complexity when the number of SM is high. This thesis proposes three new voltage balancing schemes to reduce the unnecessary switching events which are typically generated by the conventional sorting algorithm (CSA) and to reduce computational complexity: 1. The Index Selection Algorithm (ISA) is based on a constraint band of permissible voltage ripples and existing gate signals to offer three index options. This technique selects the optimum choice based on the number of SMs contained in the band. 2. The Hybrid Heap Sorting Algorithm (HSA) replaces the CSA with the heap sorting II algorithm. With this technique, the computational complexity is significantly decreased. 3. The Priority-based Sorting Algorithm (PSA) clusters the SMs of converter into different priority groups according to a pre-defined voltage ripple range along with the gate signal information of the previous sampling period. It helps to reduce the switching frequency by only selecting the necessary priority groups to be involved in the sorting stage. Another benefit of this scheme is its flexibility and great dynamic response to different pre-defined range. All the proposed algorithms produce fewer switching events and incur a lower computational cost, resulting in higher efficiency without detriment to the quality of the output waveform. The proposed voltage balancing schemes are tested using 4- and 22- level MMC models which were built using MATLAB/Simulink to investigate their performance. The converter performance is also validated for a small-scale 4-level MMC that was designed, built, and tested in the laboratory. The validation shows that the proposed algorithms clearly reduce the number of switching events. In addition, the algorithm can be easily incorporated without requiring hardware modifications.