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dc.contributor.authorQiqieh, Issa Hani Rezq Allah-
dc.descriptionPhD Thesisen_US
dc.description.abstractThere is a persistent demand for higher computational performance at low energy cost for emerging compute-intensive applications. Multipliers constitute a major component of these applications with complex logic design and a large gate count compared to other arithmetic units. As such, there is significant interest in designing new approaches to low-complexity multipliers. Approximate multiplier is a promising paradigm, which is particularly suitable for inherently imprecision-tolerant applications, such as image processing, pattern recognition and machine learning. The basic premise is to relax the precision requirements in favour of lower complexity, thereby achieving reduced circuit delay and energy consumption. This thesis presents an investigation into novel approximate multiplier design and implementation approaches. In the first approach, a multiplier design using significance-driven logic compression (SDLC) is proposed. Fundamental to this approach is a configurable lossy compression of the partial product rows. The compression is carried out by progressively replacing the exclusive- OR logic gates by low-complexity OR gates based on their bit significance. The compression is followed by commutative remapping of the resulting product terms to reduce the number of product rows. This accounts for substantially reduced number of logic cell counts and lengths of critical paths at the cost of errors in lower significant bits. In the second approach, a novel multiplier design is presented by combining a Wallace-tree accumulation method together with the SDLC. The logic compression performed by SDLC approach works for reducing the number of product rows using progressive bit significance, thereby decreasing the number of reduction stages and logic counts in accumulation. The errors introduced by lossy logic compression are minimised through a novel error compensation method (ECM). The core of this method is a parallel error detecvii tion logic used to generate error compensation bit-matrix. This matrix is then compressed using OR gates to generate an error compensation vector. To mitigate the impact of error, this vector is either considered as an additional row in the accumulation tree or used to modify an existing row. To validate the effectiveness of these approaches, a number of multipliers with different compression levels are designed and synthesized showing substantial savings in energy consumption, and reductions in critical delay and silicon area, compared to an accurate equivalent and other existing approaches. These gains are achieved at the cost of errors introduced in the circuit, which are extensively analysed. The configurable multiplier designs in the first and second approaches exhibit energy/quality trade-offs at different degrees of compression. These trade-offs can be effectively used to implement multipliers in applications, where energy can be opportunistically minimised within the envelope of quality requirements. As such, in the third study, two implementation methods are demonstrated. In the first method, a Gaussian blur filter was designed, demonstrating energy reduction with a minor loss in image quality. In the second method, the energy/quality trade-offs are leveraged in a perceptron-based machine learning application, showing energy reduction for different SDLC configurations. The proposed logic compression approach and its prototype implementations in various configurations can be suitably used for energy-efficient multiplier designs, where quality requirements can be relaxed.en_US
dc.description.sponsorshipMinistry of Higher Education and Scientific Research in Jordan and Al-Balqa’ Applied Universityen_US
dc.publisherNewcastle Universityen_US
dc.titleInvestigation into energy-efficient and approximate multiplier designen_US
Appears in Collections:School of Engineering

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