Energy-Efficient Mixed-Signal Multiplier Design using Memristive Technologies

Abstract

Energy efficiency and performance are two of the most important design considerations for computing applications, e.g., artificial intelligence at the edge and Internet of things empowered by limited energy supply from batteries or energy harvesters. For these applications, arithmetic computation is key, with multiplication and addition being the “must-have” core functionalities. Traditional approaches to these are primarily based on cascaded logic chains with long carry propagation circuits that contribute to high energy consumption and latencies. Additionally, these circuits exploit digital interfaces at both inputs and outputs, which require complex signal conversion circuits when designed using analogue methods. This thesis presents original research focused on developing low-energy and high-speed multiplication hardware. The core technology developed in this work is a novel digital-in/analogue-out mixed signal multiplication method based on a single-bit multiplication cell. The cell consists of a resistive memory bit controlled by a transistor switch. The single-bit memory cell is implemented using memristor devices, which provide non-volatile storage and avoid capacitive or inductive elements. This type of single-bit multiplication cell takes two single-bit input operands (multiplier and multiplicand). One (e.g., the multiplier) is encoded in the form of a Boolean voltage and the other (e.g., the multiplicand) is encoded in the memristor’s conductance, also set to Boolean values. The cell current then encodes the Boolean product following the Ohm’s Law. The single-bit multiplication cells are then assembled into multi-bit multipliers using a crossbar matrix structure, which directly implements the long-multiplication algorithm. Across the crossbar, Kirchhoff’s Current Law ensures that the cell currents are summed up to form the final overall product, forming a digital-in/analogue-out mixed signal design. The entire Ohm’s law-Kirchhoff’s Current Law operation is instantaneous in the absence of capacitive and inductive elements. With Kirchhoff’s Current Law,

this type of mixed-signal multiplier eliminates the need for passing carries to the left. This saves both time and energy compared with conventional digital amplifiers, which need costly and potentially long logic chains for carry handling. By using multiple memristors in an single-bit multiplication cell, costly current mirrors can be avoided from the crossbar. The core digital-in/analogue-out multiplication method can have direct applications in Internet of things nodes, like multiplying digital-to-analogue converters. One advantage of using the proposed multiplier in this application comes from the asymmetry between the two input operands. One of them, saved in memoristor conductances, is the best changed less frequently than the other, represented by voltages, precisely what an multiplying digital-to-analogue converter aims for. This digitalin/analogue-out multiplier is further developed into a digital-in/digital-out multiplier with reduced output precision, with the same bit width for both the operands and the product. We envisage our design will be useful in applications where multiple multiply-and add units are assembled into larger structures, such as in neural networks. With the same bit width for both inputs and outputs, multipliers of this design can be cascaded a straightforward manner for larger networks. The multiplier designs are implemented in 65 nm technology using Cadence Virtuoso based analogue simulations. The designs are shown to have significant speed and energy advantages over existing state of the art and the machine learning experiments demonstrate the correctness and usability of the reduced-precision multiplication scheme for artificial intelligence applications.